A Domain Speci c Language for Video Device Drivers : from Design to

Machine Program GAL Program IntelAbstractMachineAlphaAbstractMachineDeviceDriverX11InterpreterInterpreterWindows 95 Figure 3: Multiple implementations.6 Conclusions and Future WorkDomain speci c languages hold the promise of de-livering high payo s in terms of software reuse, au-tomatic program analysis, and software engineering.In this paper we have presented GAL, an exampleof a complete DSL for a realistic program family:video device drivers. We also demonstrated the ben-e ts of DSLs by showing how GAL raises the level ofabstraction of device driver speci cations and iden-tifying some analyses that can be performed on GALspeci cations because it is domain speci c.A further contribution of the paper is to validateour framework of application generator design byapplying it to this program family to provide animplementation of GAL. Since our implementationis based on partial evaluation, it provides a com-plete interpreter for prototyping device drivers, butstill automatically generates e cient device drivers.E ciency is demonstrated with results comparinghand-coded drivers to automatically generated de-vice drivers. Generated drivers are roughly one thirdlarger than hand-code drivers and perform equiva-lently in terms of speed. Additionally, we give mea-sures on expected reuse bene ts; GAL speci cationsare roughly a factor of 9 smaller than a driver hand-coded in C.Although our framework signi cantly reduces thedevelopment time of application generators, futurework could be done in this direction. Speci -cally, this approach would bene t from a generator-speci c reuse method that would allow interpretersand abstract machines to be constructed from reusedcomposable parts. Additionally, given the natureof DSLs, they are extended frequently to adapt tonew program requirements, and the ease of exten-sion also needs to be considered for such languagecomponents.Our implementation of the static analyses indi-cates that methods of quickly constructing staticanalyses should also be investigated (e.g., compos-able analyses). This is more important for DSLsthan GPLs, since static analyses are a major moti-vation of the approach.In this work we have presented an application ofour approach to a program family with existing fam-ily members. To further validate the approach, it isalso important to study its application to a programfamily which is not pre-existing. In this case, theabstract machine and DSL might be developed fromthe results of a domain analysis or a commonalityanalysis, such as FAST [12].References[1] B.R.T. Arnold, A. van Deursen, and M. Res.An algebraic speci cation of a language describ-ing nancial products. In M. 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Inthis appendix, we explain some of the constructs that were not included in the main text.Although the various registers of video cards are typically accessed using an addressing scheme, there issometimes a sequential procedure that must be followed to access some registers. The serial construct isused to specify this kind of procedure (see listing). The construct consists of a list of sequences of actionsthat should be performed on the ports to access the registers. Thus multiple ports may be accessed duringthe procedure, as in the example. Each sequence consists of a port, an operation (<= write, <=> read/write,=> read), and a sequence of values for writes or registers names for reads and read/writes. The actions inthe sequence are performed from the rst port to the last, from left to right in the sequence. The mode (Rread, R/W read/write, W write) to the right of the sequence indicates whether this sequence applies to readingthe registers to writing the registers or both.The serial construct in the example de nes the registers PLL1, and PLL2. In order to write values to theseregisters the construct would be executed as follows. Write 3 to misc[3..2], write the value of PLL1 toseq(0x12), write the value of PLL2 to seq(0x13), and nally, write 0, then 1, then 0 to seq(0x15)[5].The S3 speci cation also includes an example of a derived eld, which is not discussed in the paper. Thisis a eld whose value is derived from one of the standard elds. In the example, StartFIFO is a derivedeld. Its value is set whenever the graphics mode is set, and is based on the value of HTotal, the horizontalresolution. The declaration indicates this with the from clause.The clockmap is used when a card has both xed and programmable clocks such as the S3 Trio cards. Itindicates which clocks are xed and which are programmable. The example for the S3 indicates that clock0 and 1 are xed, clock 2 is not available (NA), and clock 3 is the programmable clock f3. The parametersMinPClock and MaxPClock are also related to clocks and specify the minimum and maximum values thatcan be generated by the clock (i.e. not all values of f3M, f3N1, and f3N2 are valid).Finally, the operating mode access is used to lock an unlock registers on the card.B GAL S3 Listing-List all cards/models supported by this driver.chipsets S3_911,S3_924,S3_80x,S3_928,S3_864,S3_964,S3_866,S3_868,S3_968,S3_TRIO32,S3_TRIO64;-Define ports.port svga indexed:=0x3d4;port seq indexed:=0x3c4;port misc := 0x3cc, 0x3c2;-Define registers.register Miscr:=misc;register Slock:=seq(0x8);register Offset:=svga(0x13);register ExtChipID:=svga(0x2e);register ChipID:=svga(0x30);register Memory:=svga(0x31);register State:=svga(0x36);register Lock1:=svga(0x38);register Lock2:=svga(0x39);register StartFIFOr:=svga(0x3B);register Misc1:=svga(0x3a);register Control:=svga(0x42);register Control2:=svga(0x51);register HOverflow:=svga(0x5D); register VOverflow:=svga(0x5E);register Control3:=svga(0x69);-Serial registers (see appendix A).serial beginmisc[3..2]<= (3,,-,-,-) W;seq(0x12)<=> (-,PLL1,-,-,-) R/W;seq(0x13)<=> (-,PLL2,-,-,-) R/W;seq(0x15)[5]<=(-,,0,1,0) W;end;-Define predefined fields-Horizontal resolution fields.field HTotal := HOverflow[0]#std;field HEndDisplay := HOverflow[1]#std;field HStartBlank := HOverflow[2]#std;field HStartRetrace := HOverflow[4]#std;-Vertical resolution fields.field VTotal := VOverflow[0]#std;field VEndDisplay := VOverflow[1]#std;field VStartBlank := VOverflow[2]#std;field VStartRetrace := VOverflow[4]#std;-Virtual screen fields.field LogicalWidth := Control2[5..4]#Offset scaled 8;casesfor S3_928,S3_968,S3_TRIO32,S3_TRIO64field StartAddress := Control2[1..0]#Memory[5..4]#std;for S3_80xfield StartAddress := Control2[0]#Memory[5..4]#std;for S3_864,S3_964field StartAddress := Control3[4..0]#std;for othersfield StartAddress := Memory[5..4]#std;end;-Define derived fields (see appendix A).field StartFIFO from HTotal := HOverflow[6]#StartFIFOr offset 10 scaled 8;-Special S3 flags that must be set for 256 color graphics modes.enable SVGAMode sequence is Misc1[4]<=1,Memory[3]<=1;-Define standard parameters.param TwoBankRegisters:=false;param InterlaceDivide := true;casesfor S3_911,S3_924param RamSize:=State[5] mapped (0=>1024,1=>512);for othersparam RamSize:=State[7..5] mapped (0=>4096,2=>3072,3=>8192,4=>2048,5=>5120,6=>1024,7=>512);end; -Define clocks.casesfor S3_TRIO32,S3_TRIO64param NoClocks:=4;field ClockSelect:=Miscr[3..2];param MinPClock:=135;param MaxPClock:=270;field f3M:=PLL2[6..0] offset 2 range 1 to 127;field f3N1:=PLL1[4..0] offset 2 range 1 to 31;field f3N2:=PLL1[6..5] mapped (0=>1,1=>2,2=>4,3=>8);clock f3 is 14318*f3M / f3N1*f3N2;clockmap is (fixed,fixed,NA,f3);for othersparam NoClocks:=16;field ClockSelect:=Control[3..0];end;-Identification procedure.identification begin1: ChipID[7..4] => (0x8=>step 2, 0x9=>S3_928, 0xA=>S3_80x, 0xB=>S3_928,0xC=>S3_864, 0xD=>S3_964, 0xE=>step 3);2: ChipID[1..0] => (0x1=>S3_911,0x2=>S3_924);3: ExtChipID => (0x10=>S3_TRIO32, 0x11=>S3_TRIO64, 0x80=>S3_866,0x90=>S3_868, 0xB0=>S3_968);end;-Register locks on S3 chips.enable access sequence is Lock1<=0x48,Lock2<=0xA5,Slock<=0x6;disable access sequence is Lock1<=0x00,Lock2<=0x5A,Slock<=0x0;